Semiconductor memory device

ABSTRACT

A semiconductor memory device (10), including a conventional redundancy memory array (12) therein, is disclosed. The redundancy memory array (12) is used for compensating data being stored in a defective memory cell (13&#39;) of main memory cells (11) located in the memory device (10). An addressing device (15) for specifying one of the memory cells, activates both the main memory cells (11) and the redundancy memory array (12), and at the same time, both a detecting device (16) for detecting whether or not an address information (AI) to be supplied to the addressing device (15) specifies the defective memory cell (13&#39;), and a switching device (17) for selecting either one of the systems of the main memory cells (11) and the redundancy memory array (12), in accordance with a resultant determination of the detecting device (16), are activated. The switching device (17) is connected between a main data bus (DB m ), cooperating with the main memory cells (11), and a redundancy data bus (DB r ), cooperating with the redundancy memory array (12).

DESCRIPTION BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device and, moreparticularly, relates to a semiconductor memory device including atleast one redundancy memory array therein.

A semiconductor memory device is mainly comprised of many memory cellsarranged along both rows and columns in an orthogonal fashion. Each ofthe memory cells stores a respective bit of data. Each bit of data to bewritten or read is located at a corresponding memory cell which isspecified by an address information. The address information determinesboth a row address and a column address so that the desired one of thememory cells can be accessed at the intersect portion of both thedetermined row and column addresses.

Generally, an undesired defect is often created in one of the greatnumber of memory cells, during the manufacturing process of the memorydevice. It is, of course, obvious that the memory device cannot operatenormally when the memory device includes such a defective memory celltherein. Therefore, such a memory device cannot be put into practicaluse, and such a memory device must be left out. However, it is notpreferable, from an economical point of view, to leave out themanufactured memory device due to the presence of only one defectivememory cell among a great number of memory cells.

In order to save such a defective memory device, the redundancy memoryarray is usually incorporated with the main memory cells. When saidaddress information specifies a row memory array or a column memoryarray, including the defective memory cell, such defective row or columnmemory array is replaced by the redundancy memory array which contains acorrected memory cell with regard to the defective memory cell of themain memory cells.

A conventional semiconductor memory device, including such a redundancymemory array, is comprised of the main memory cells, an addressing meansfor specifying both the row memory array and the column memory array ofthe main memory cells, a detecting means for detecting whether or notthe addressing means specifies the row or column memory array includingthe defective memory cell therein and a switching means for replacingthe specified row or column memory array by the redundancy memory array,according to the result of the detecting means. Above all, the presentinvention refers specifically to an improvement of the switching meansand the switching procedure. In the above mentioned conventionalsemiconductor memory device, first, the detecting means is activated forinspecting the address information to be applied to the addressingmeans, but, the addressing means is not yet activated; second, if thedetecting means determines that the address information does not specifythe row or column memory array including the defective memory cell, theaddressing means starts being activated and accesses the specifiedmemory cell; alternatively, if the detecting means determines that theaddress information specifies the row or column memory array, includingthe defective memory cell, the addressing means is not yet activated,but, the switching means activates the redundancy memory array in placeof the defective memory array of the main memory cells and; last, theoutput data to be read is produced from the specified memory cell to adata output buffer circuit via a data bus or, if necessary, the inputdata to be written is supplied from a data input buffer circuit to thespecified memory cell via the data bus.

Thus, the above mentioned memory device of the prior art has ashortcoming, in that the access time for reading or writing the data islong, and accordingly a high speed operation of the semiconductor memorydevice cannot be expected. This is because, a time for inspecting theaddress information, by means of the detecting means, must be insertedprior to each time the accessing operation for the main memory cells iscarried out.

SUMMARY OF THE INVENTION

An object of the present invention is, therefore, to provide asemiconductor memory device, including a redundancy memory arraytherein, which has no shortcoming similar to the aforesaid shortcomingof such semiconductor memory device of the prior art, and accordingly,high speed operation of the semiconductor memory device, including theredundancy memory array therein, can be obtained.

According to the present invention, there is provided a semiconductormemory device, including a redundancy memory array therein, wherein boththe main memory cells and the redundancy memory array can be accessedsimultaneously by using the same address information, regardless ofwhether the address information specifies a defective memory cell. Thenthe data to be read, from the main memory cells, appears on a main databus and, at the same time, corresponding data to be read from theredundancy memory array appears on a redundancy data bus. These main andredundancy data buses are connected via the switching means. Theswitching means selectively connects the main or redundancy data bus tothe data output buffer circuit according to a result of the detectingmeans for inspecting whether the address information specifies adefective memory cell of the main memory cells. If the main memory cellsare fabricated as an RAM (random access memory), the data to be writtenfrom the data input buffer circuit is selectively supplied to the mainor redundancy data bus via the switching means under the control of thedetecting means.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically illustrating a basic embodimentaccording to the present invention;

FIG. 2 illustrates a circuit diagram of a first embodiment, based onsaid the embodiment of FIG. 1, according to the present invention;

FIGS. 3A and 3B depict schematic timing charts, used for explaining theoperation of a semiconductor memory device 20 shown in FIG. 2;

FIG. 4 illustrates a circuit diagram of a second embodiment, based onthe basic embodiment of FIG. 1, according to the present invention;

FIG. 5 depicts schematic timing charts, used for explaining theoperation of a semiconductor memory device 40 shown in FIG. 4; and

FIG. 6 is a circuit diagram illustrating one example of a detectingdevice 16.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will become more apparent from the detaileddescription of the preferred embodiments presented below, with referenceto the accompanying drawings.

Referring to FIG. 1, which is a block diagram schematically illustratinga basic embodiment according to the present invention, the referencenumeral 11 represents main memory cells. The main memory cells 11coordinates with a redundancy memory array 12. The memory cells 11 andthe array 12 are comprised of a plurality of memory cells 13. In themain memory cells 11, the memory cells 13 are arranged along row memoryarrays and column memory arrays in an orthogonal fashion. However, theredundancy memory array 12 is comprised of a single row memory array ora single column memory array (in this Figure, for example, a singlecolumn memory array is illustrated). If the main memory cells 11contains a column memory array (or row memory array) 14 which includes adefective memory cell (x ) 13', the defective column memory array 14 isfabricated, in advance, as the redundancy memory array 12 which containsa corrected memory cell (o ) 13" therein. Accordingly, if the defectivecolumn memory array 14 (or a defective row memory array) is specified byan addressing means 15 in accordance with an address information AI tobe supplied from, for example, a central processing unit (not shown),the specified defective column memory array 14 must be replaced by theredundancy memory array 12.

According to the present invention, a switching means 17 is located inthe data buses. The data buses are comprised of a main data bus DB_(m),cooperating with the main memory cells 11, and a redundancy data busDB_(r), cooperating with the redundancy memory array 12. A contact K_(m)of the switching means 17 is connected to the bus DB_(m) and a contactK_(r) thereof is connected to the bus DB_(r). The separated data busesDB_(m) and DB_(r) also create one of the features of the presentinvention.

If the addressing information AI specifies a normal column memory arrayand also a normal row memory array, normal data is produced on the databus DB_(m) and transferred to a data output buffer circuit (DOB) 18, viathe contact K_(m) of the switching means 17 and a data bus DB, so thatan output data D_(out) is obtained. Contrary to this, if the addressinginformation AI specifies a defective column memory array 14, theaddressing means 15 specifies not only the array 14, but also theredundancy memory array 12, simultaneously, which fact is also anotherof the features of the present invention. In this case, both thedefective data and the normal data are produced, simultaneously, on thedata bus DB_(m) and the data bus DB_(r), respectively. Therefore, thecontact K_(m) of the switching means 17 is made to open and the contactK_(r) thereof is made to close, so as to obtain only the normal datafrom the data bus DB_(r). The switching operation of the contacts K_(m)and K_(r) is achieved by means of a detecting means 16. The detectingmeans 16 holds therein the same address information as the informationAI regarding the defective column memory array 14 (or the defective rowmemory array) and always operates to compare the address information AIwith the held address information regarding the defective memory arrayof the main memory cells 11. When both the address information setscoincide with each other, the detecting means 16 operates to switch thecontact K_(m) to the contact K_(r).

If a semiconductor memory device 10 is fabricated as the RAM, an inputdata D_(in) to be written is applied to the data bus DB_(m) or DB_(r),via a data input buffer circuit (DIB) 19, the data bus DB and theswitching means 17. If the input data D_(in) is data to be written inone of the memory cells 13 other than the defective memory cell 13', thedetecting means 16 controls the switching means 17, so as to close thecontact K_(m) in accordance with the address information AI regardingthe data D_(in). Contrary to this, if the data D_(in) is data to bewritten in the defective memory cell 13', the detecting means 16controls the switching means 17 so as to close the contact k_(r), sothat the data D_(in) is stored at the corresponding normal memory cell13".

The semiconductor memory device 10 can overcome the previously mentionedshortcoming created by the prior art memory device. That is, the accesstime, achieved by the device 10, is shorter than that of the prior artdevice, and accordingly a high speed memory device can be obtained. Thereason for this fact has already been explained, but will be mentionedagain with reference to FIG. 1. In the prior art, the addressing means(corresponding to the means 15) is not activated even though the addressinformation AI has already been applied thereto. That is, the addressingmeans cannot be activated until the detecting means (corresponding tothe means 16) determines whether the memory cell 11 should be accessedor the memory array 12 should be accessed, through the operation ofinspecting the address information AI. Thus, the time for carrying outsuch an inspection of the address information, expands the total accesstime of the prior art memory device. However, according to the presentinvention, such a time for inspecting the address information AI doesnot exist independently, but exists in parallel with a so-called realtime operation for accessing both the memory cells 11 and the memoryarray 12, simultaneously.

FIG. 2 illustrates a circuit diagram of a first embodiment, based on thebasic embodiment of FIG. 1, according to the present invention. Themembers, represented by the same numerals and symbols as those of FIG.1, are identical to each other. In FIG. 2, the reference numeral 20represents a semiconductor memory device of the first embodiment. Thereference symbols R1, R2 through Rn represent row lines, that isso-called word lines, the reference symbols C11, C12, C21, C22 throughCm1, Cm2 represent column lines, that is so-called bit lines, and aplurality of memory cells 13 are connected at every intersection pointof these row and column lines. Each of these memory cells 13 may befabricated by a dynamic memory element, such as a so-called singletransistor cell. The single transistor cell is comprised of a singleMOS·FET (metal-oxide semiconductor·field effect transistor) and acapacitor, such as shown in the U.S. Pat. No. 4,025,907. However, eachof these memory cells 13 can also be fabricated by a static memoryelement. The dynamic memory element and the static memory element willbe mentioned hereinafter when a second embodiment of the presentinvention is explained. At the ends of the pairs of the column lines,conventional sense amplifiers (SA1, SA2 . . . SAm) 21-1, 21-2 through21-m are connected. While, at the other ends of these column lines,conventional transfer gates 22-1, 22-2 through 22-m, made of, forexample pairs of FETs, are connected. The column lines C11, C12 throughCm1 and Cm2 are connected to the main data bus DB_(m) (see FIG. 1), viathese transfer gates 22-1 through 22-m. The control gates of the FETs,comprising the transfer gates 22-1 through 22-m, are connected to acolumn decoder (COLUMN DEC) 23 for selecting one of the column lines(column memory arrays). Both the column decoder 23 and a row decoder(ROW DECODER) 24, as one body, form the aforesaid addressing device 15of FIG. 1. The row decoder 24 functions to select one of the row lines(row memory arrays). As previously mentioned, the data to be read is,first, provided on the bus DB_(m) and, then, obtained from, as theoutput data D_(out), the data output buffer circuit 18, via theswitching means 17 and the common bus DB. When, for example, the rowline R2 becomes logic "1" and the voltage level of one of the columnlines C21 and C22 becomes higher than that of the other column line, inaccordance with the stored data in the memory cell 13-22, a flip-flop(not shown) of the sense amplifier 21-2 changes its status so as toamplify the difference of voltage levels between the column lines C21and C22. The amplified difference of the voltage levels is transferredto the data bus DB_(m) via the transfer gate 22-2, which is now made toopen, and finally obtained, as the output data D_(out).

The redundancy memory array 12 of FIG. 2 is fabricated as a columnmemory array, which also has column lines Ck1 and Ck2. At the end ofthese column lines, a sense amplifier (SAk) 21-k is connected, while, atthe other end thereof, the aforesaid redundancy data bus DB_(r) (seeFIG. 1) is connected. The buses DB_(m) and DB_(r) are selectivelyconnected to the common data bus DB, via the switching means 17, undercontrol of the detecting means 16. The detecting means 16 produces botha first output P and a second output P having an inverted level of theoutput P. The levels of the outputs P and P vary in accordance with theaddress information AI. Thus, in the switching means 17, either one of atransfer gate 25_(m) or a transfer gate 25_(r) opens, selectively,according to the levels of the outputs P and P.

As previously mentioned, the defective memory cell is often createdduring the manufacturing process of the memory device 20. Then, acorresponding column memory array of the main memory cells 11,containing a corrected memory cell, is formed as the memory array 12. Atthis time, the column address information of the above mentioneddefective column memory array, is written in the detecting means 16. Innormal operation, the detecting means 16 produces the outputs P havinglogic "1" and P having logic "0", and accordingly the common data bus DBis connected, not to the bus Db_(r), but to the bus DB_(m). However, ifthe detecting means 16 determines that the presented address informationAI coincides with the address information written therein, the detectingmeans 16 produces the outputs P having logic "0" and P having logic "1",and accordingly, the common data bus DB is connected to the data busDB_(r) so as to replace the data, produced from the defective columnmemory array, by the data produced from the redundancy column memoryarray 12. The details of the detecting means 16 will be mentionedhereinafter.

The above mentioned operation for reading the data will be clarifiedwith reference to FIGS. 3A and 3B. FIG. 3A depicts schematic timingcharts used for explaining a normal operation of the semiconductormemory device 20, while, FIG. 3B depicts schematic timing charts usedfor explaining an operation thereof when the redundancy memory array 12is selected. Referring to both FIGS. 3A and 3B, first, the addressinformation AI provides both the row address information RA and thecolumn address information CA (see step 1 ). Second, the row decoder 24is activated by the address information RA (see step 2 ) immediatelyafter the occurrence of the step 1 . Third, the column decoder 23 isactivated by the address information CA (see step 3 ). It should benoted that, in the usual memory device, the row memory array and thecolumn memory array are selected, not simultaneously, but sequentiallyone by one with some delay of time T_(d). During the delay of the T_(d),that is the activation of the row decoder 24, the detecting means 16 andthe switching means 17 are activated (see step 2 '). If the resultantdetermination of the detecting means 16 indicates that the columnaddress information CA does not specify the defective column memoryarray, the outputs P and P from the detecting means 16 are left as theyare (see P and P in FIG. 3A). Finally, the accessed data sets D and D(see FIGS. 2 and 3A) are produced from the circuit 18, as the outputdata D_(out).

Contrary to the above, if the resultant determination of the detectingmeans 16 indicates that the column address information CA specifies adefective column memory array, the levels of the outputs P and P areexchanged, such as shown in FIG. 3B, and thereby the corrected data setsD and D are produced from the circuit 18.

FIG. 4 illustrates a circuit diagram of a second embodiment, based onthe basic embodiment of FIG. 1, according to the present invention. Themembers, represented by the same reference numerals and symbols, arethose of FIG. 2. In FIG. 4, the reference numeral 40 represents asemiconductor memory device of the second embodiment. Memory cells 43and 43d comprising the main memory cells 11 are made of singletransistor cells, each of which has an MOS·FET and a capacitor. Thememory cells 43d are so-called dummy memory cells.

The redundancy memory array 12 of FIG. 4 is fabricated, not as a columnmemory array, as shown in the first embodiment, but as a row memoryarray. In the array 12, a plurality of memory cells 53 are arranged,such as shown in this FIG. 4. The memory cells 53 are not made ofdynamic memory elements (cells), but of static memory elements (cells).Each of the static memory cells 53 is comprised of driver transistorsQ₁, Q₂, a load L and gate transistors Q₃, Q₄. The gate transistors Q₃and Q₄ are made to go ON and OFF by the corresponding one of the outputsfrom the column decoder 23. Row lines R_(r1) and R_(r2), also acting asthe redundancy data bus DB_(r), are connected or disconnected to boththe data output buffer circuit 18 and data input buffer circuit 19, viathe common data bus DB, under control of the transfer gate 25_(r) of theswitching means 17. Similarly, the main data bus DB_(m) is connected ordisconnected to both circuits 18 and 19, via the bus DB, under controlof the transfer gate 25_(m) of the switching means 17. These gates25_(m) and 25_(r) are selectively made to go ON or OFF, according to theoutputs P and P from the detecting means 16. In this case, the rowaddress information of the defective row memory array, containing thedefective memory cell therein, is written in the detecting means 16.

The operation of the semiconductor memory device 40 will be clarifiedwith reference to FIG. 5. In FIG. 5, which depicts schematic timingcharts used for explaining the operation thereof, the addressinformation AI (see FIG. 4) sequentially provides, first, the rowaddress information RA and, second, the column address information CA(see row c)). The operations for fetching the address information RA andCA, are started when a row address strobe signal RAS and a columnaddress strobe signal CAS, become logic "0", respectively (see rows (a)and (b)). Then the row decoder 24 (FIG. 4) is activated according to theaddress information RA (see step 1 or row (d)) and the voltage level ofthe corresponding row line increases (see step 2 of row (d)). At thesame time, the detecting means 16 (FIG. 4) starts the operation fordetermining whether or not the presented address information RAcoincides with the defective row memory array. At the beginning of theoperation for inspecting the address information RA, the logic of theoutputs P and P are "1" and "0", respectively, as shown in rows (e) and(f).

When the voltage level of the row line becomes "H" (high), the senseamplifier (SA) is activated by a clock pulse LE (see row (d)), and oneof the corresponding pair of column lines is caused to be the "H" level,while, the other thereof is caused to be the "L" level. As known fromthe aforesaid U.S. Pat. No. 4,025,907, in the single transistor celltype of memory cell, the column lines are precharged to a voltage levelof "V" before the operation for read is commenced. Since the capacitancevalue of the dummy memory cell 43d (FIG. 4) is selected to be one halfof the capacitance value of the real memory cell 43 (FIG. 4), if thereal memory cell 43 has a stored data "1" and the cell 43 is prechargedto the voltage level of "V", the voltage level of the column line doesnot vary even though the real memory cell is specified and connected tothis column line. On the other hand, when the column line is connectedto the dummy memory cell 43d which has been discharged, the voltagelevel of this column line is reduced to the level of "V₁ " (V₁ <V).Thus, the outputs of the sense amplifier (SA), made of a flip-flop,change, at the real memory cell side, to OFF ("H" level) and change, atthe dummy memory cell side, to ON ("L" level). However, since thedifference of voltage levels, between the pair of the column lines, isvery small, it takes a very long time to complete the changes (see SA ofrow (d)) of the outputs of the sense amplifier (SA). This is theshortcoming of the single transistor cell type memory cell; but, thistype memory cell has an advantage in that it is very simple inconstruction and enables a higher packing density.

Accordingly, the detecting means 16 (FIG. 4) and the switching means 17(FIG. 4) can finish respective operation during the above mentioned longtime for completing the changes of the outputs of the sense amplifier(SA) (see FIG. 5 rows (e) and (f)). In this case, the redundancy memoryarray 12 must finish its work very quickly by the time the columnaddress strobe signal CAS (see row (b)) changes to logic "0". Therefore,each memory cell 53 (FIG. 4) of the redundancy memory array 12 is madeof, not the single transistor cell type memory cell, but of a high speedstatic memory element, such as a flip-flop type memory cell. Thereafter,the column decoder 23 (FIG. 4) is activated according to the columnaddress information CA (see step 3 of row (d)), and the desired data isprovided on the data bus (see step 4 of row (d)). Finally, the outputdata D_(out) is produced (see step "D_(out) " of row (d)) from the dataoutput buffer circuit 18 (FIG. 4).

FIG. 6 is a circuit diagram illustrating one example of the detectingmeans 16. In the detecting means 16, the reference numerals 61-1, 61-2,61-3, 61-4 through 61-S represent fuse elements. FETs 62-1, 62-2, 62-3,62-4 through 62-S are connected, in series, with the respective fuseelements. These series connected fuse elements and FETs are connected inparallel between a common signal line L and a ground line GND. Since thedetecting means 16 is fabricated as a PROM (programmable read onlymemory), particular fuse elements have been melted away, in advance.That is, a very high power is supplied from a pad 63, which is locatedon the same single semiconductor chip for mounting the semiconductormemory device of the present invention. At the same time, particularFETs are made conductive, and accordingly, the corresponding particularfuse elements are melted away by the high power from the pad 63. Theparticular FETs are defined by an input address (A₀, A₀, A₁, A₁ . . .A₈) which is the same as the row address information (RA) or the columnaddress information (CA), regarding the defective row or column memoryarray of the main memory cells 11.

Thus, the fabricated PROM, that is the detecting means 16, operates asfollows. The common signal line L is precharged to a voltage level ofabout "V_(DD) " via an FET 64 sequentially in synchronism with a clocksignal φ_(P). Then, if the address information AI, supplied to the PROM(16), specifies one of the normal address arrays, containing nodefective memory cell, at least one of the pairs of the fuse element andthe FET becomes conductive. Therefore, the level of the line L isreduced to the ground level (GND) (at this time, the FET 64 is made togo OFF by the clock signal φ_(P)). Thus, an FET 65 is not made to go ON,and, on the other hand, the ground voltage level, supplied through anFET 66 (which is now made conductive by a clock signal φ_(R)), causesthe output P to become the logic "0" and the output P the logic "1", viaan inverter 67. In this case, the transfer gate 25_(m) (see FIGS. 2 and4) is opened.

However, if the address information AI, supplied to the PROM (16),specifies the defective memory array, since all the FETs connected tothe respective fuse elements which have been melted away are madeconductive, and all the remaining FETs connected to the respective fuseelements which are not melted away are made non-conductive, the voltagelevel of nearly "V_(DD) " on the line L, causes the FET 65 to beconductive, and accordingly the output P becomes logic "1" and theoutput P becomes logic "0" (the FET 66 is now non-conductive). In thiscase, the transfer gate 25_(r) (see FIGS. 2 and 4) is opened.

The above mentioned explanations are made by taking, as an example, acase where only one defective memory cell exists in the main memorycells 11 for the purpose of facilitating the understanding of thepresent invention. However, it should be understood that the presentinvention can also be applicable to a memory device containing two ormore defective memory cells or one or more defective memory arraystherein. Further, the above mentioned explanations are made by taking asan example a case where the redundancy memory array 12 is fabricated aseither one of the row or column memory arrays. However, it should beunderstood that the present invention may be applicable to a memorydevice which cooperates with both the redundancy row and column memoryarrays.

I claim:
 1. A semiconductor memory device, operatively connectable toreceive address information including both row and column addressinformation, comprising:a data bus; a main memory array, operativelyconnected to said data bus and having main memory cells, a main rowmemory array and a main column memory array, one of the main memorycells is a defective memory cell; a redundancy memory array, operativelyconnected to said data bus, being associated with said main memory cellsand containing therein a corrected memory cell corresponding to saiddefective memory cell contained in said main memory cells; addressingmeans, operatively connected to said main memory cells and saidredundancy memory array, and operatively connectable to receive theaddress information, for specifying said main memory array containing adesired memory cell in dependence upon the address information, saidaddressing means comprising a row decoder operatively connected to saidmain memory array, and a column decoder operatively connected to saidmain memory array, for specifying the main row memory array and the maincolumn memory array of said main memory array, and the row addressinformation being applied to said row decoder and column addressinformation being applied to said column decoder; detecting means,operatively connected to receive the address information, for detectingwhether or not said address information specifies said defective memorycell; switching means, operatively connected to said data bus and saiddetecting means, for selecting one of said main memory array and saidredundancy memory array, in dependence upon a resultant determination ofsaid detecting means; a data input buffer circuit operatively connectedto said data bus; and a data output buffer circuit operatively connectedto said data bus; so as to read true data, via said data bus, from saiddata output buffer circuit or to write true data, via said data bus,from said data input buffer circuit, said data bus comprising:a maindata bus operatively connected to said main memory array and said mainmemory cells therein; a redundancy data bus operatively connected tosaid redundancy memory array; and a common bus operatively connected tosaid data input buffer circuit and said data output buffer circuit; saidswitching means operatively connected between said main data bus andsaid redundancy data bus, so that either one of these data buses isselectively connected by said switching means, via said common bus, tosaid data output buffer circuit or said data input buffer circuit; andsaid addressing means specifying both said main memory array having saidmain memory cells and said redundancy memory array, simultaneously, saidswitching means being activated in parallel with the operation of saidaddressing means.
 2. A semiconductor memory device as set forth in claim1, wherein said redundancy memory array comprises a redundancy columnmemory array and wherein specified memory cells of both the main rowmemory array and said redundancy memory array are accessed by said rowdecoder, simultaneously.
 3. A semiconductor memory device as set forthin claim 2, wherein said detecting means and said switching means areactivated, in dependence upon said column address information.
 4. Asemiconductor memory device as set forth in claim 1, wherein said memorycells and said redundancy memory array comprise dynamic memory elements.5. A semiconductor memory device as set forth in claim 1, wherein saidmain memory cells comprise dynamic memory elements and said redundancymemory array comprises static memory elements.
 6. A semiconductor memorydevice as set forth in claim 1,wherein said detecting means comprises aprogrammable read only memory, operatively connected to said switchingmeans and operatively connectable to receive address information,wherein an address of data to be written is defined by said columnaddress information and specifies the column memory array containingsaid defective memory cell therein, and wherein said programmable readonly memory activates said switching means when the corresponding columnaddress information is applied to said programmable read only memory. 7.A semiconductor memory device as set forth in claim 1, wherein said mainmemory cells and said redundancy memory array comprise static memoryelements.
 8. A semiconductor memory device operatively connectable toreceive address information, comprising:a data bus; a main memory array,operatively connected to said data bus and having main memory cells, oneof which is a defective memory cell said main memory array also includesa main column memory array and a main row memory array; a redundancymemory array, operatively connected to said data bus, being associatedwith said main memory cells and containing therein a corrected memorycell corresponding to said defective memory cell contained in said mainmemory cells, said redundancy memory array also includes a redundancyrow memory array; addressing means, operatively connected to said mainmemory cells and said redundancy memory array, and operativelyconnectable to receive the address information, for specifying said mainmemory array containing a desired memory cell, in dependence upon theaddress information, said addressing means comprising a row decoder anda column decoder for specifying the main row memory array and the maincolumn memory array of said main memory array; detecting means,operatively connectable to receive the address information, fordetecting whether said address information specifies said defectivememory cell; switching means, operatively connected to said data bus andsaid detecting means, for selecting one of said main memory array andsaid redundancy memory array in dependence upon a resultantdetermination of said detecting means; a data input buffer circuitoperatively connected to said data bus; and a data output buffer circuitoperatively connected to said data bus; so as to read true data, viasaid data bus, from said data output buffer circuit or to write truedata, via said data bus, from said data input buffer circuit, said databus comprisinga main data bus operatively connected to said main memoryarray and said main memory cells therein; a redundancy data busoperatively connected to said redundancy memory array; and a common busoperatively connected to said data input buffer circuit and said dataoutput buffer circuit; said switching means operatively connectedbetween said main data bus and said redundancy data bus, so that eitherone of these data buses is selectively connected by said switchingmeans, via said common bus, to said data output buffer circuit or saiddata input buffer circuit; and said addressing means specifying bothsaid main memory array having said main memory cells and said redundancymemory array, simultaneously, said switching means being activated inparallel with the operation of said addressing means, and said addressinformation sequentially provides, first, the row address information tobe applied to said row decoder and then the column address informationto be applied to said column decoder.
 9. A semiconductor memory deviceas set forth in claim 8, wherein specified memory cells of both the maincolumn memory array and said redundancy row memory array are accessed bysaid column decoder, simultaneously.
 10. A semiconductor memory deviceas set forth in claim 9, wherein said detecting means and said switchingmeans are activated, in dependence upon said row address information,during the activation of said row decoder, in dependence upon said rowaddress information, and until said column address information isprovided again.
 11. A semiconductor memory device as set forth in claim8, wherein said detecting means comprises a programmable read onlymemory, operatively connected to said switching means and operativelyconnectable to receive address information, an address of data to bewritten is defined by said row address information and specifies the rowmemory array containing said defective memory cell therein, and theprogrammable read only memory activates said switching means when thecorresponding row address information is applied to said programmableread only memory.
 12. A semiconductor memory device as set forth inclaim 6 or 11,wherein said programmable read only memory generates afirst output and a second output having an inverted level with respectto said first output, wherein said switching means comprises a firstpair of field effect transistors operatively connected to said main databus and said common data bus and a second pair of field effecttransistors operatively connected to said redundancy data bus and saidcommon data bus, and wherein said first and second pairs of field effecttransistors are made to go ON and OFF alternatively in dependence uponthe first output and the second output having the inverted level of saidfirst output, both outputs being generated by said programmable readonly memory, simultaneously.
 13. A semiconductor memory device,operatively connectable to receive an address signal, comprising:a mainmemory array including a main row memory array and a main column memoryarray, and having therein a potentially defective memory cell having amain memory defective cell address; a redundancy column memory arrayhaving therein a redundant memory cell for replacing said potentiallydefective memory cell of said main column memory array; decoding means,operatively connected to said main memory array and said redundancycolumn memory array, and operatively connectable to receive the addresssignal, for decoding said address signal and for specifying a memorycell to be accessed in said main memory array and said redundancy columnmemory array; detecting means, operatively connectable to receive theaddress signal, for generating a switching signal when the addresssignal corresponds to the main memory defective cell address; andswitching means, operatively connected to said detecting means, saidmain memory array and said redundancy column memory array, for switchingbetween said main memory array and said redundancy column memory arrayin dependence upon the switching signal and for passing therethroughdata to be stored in or retrieved from said semiconductor memory device,said switching means selecting said redundancy column memory array forstorage and retrieval when the address signal specifies the main memorydefective cell address, and said decoding means and said detecting meansreceiving the address signal simultaneously, so that detection occurscoincident with decoding.
 14. A semiconductor memory device, operativelyconnectable to receive an address signal, comprising:a main memory arrayincluding a main column memory array and a main row memory array, andhaving therein a potentially defective memory cell having a main memorydefective cell address; a redundancy row memory array having therein aredundant memory cell for replacing said potentially defective memorycell of said main row memory array; decoding means, operativelyconnected to said main memory array and said redundancy row memory arrayand operatively connectable to receive the address signal, for decodingsaid address signal and for specifying a memory cell to be accessed insaid main memory array and said redundancy row memory array; detectingmeans, operatively connectable to receive the address signal, forgenerating a switching signal when the address signal corresponds to themain memory defective cell address; and switching means, operativelyconnected to said detecting means, said main memory array and saidredundancy row memory array, for switching between said main memoryarray and said redundancy row memory array in dependence upon theswitching signal and for passing therethrough data to be stored in orretrieved from said semiconductor memory device, said switching meansselecting said redundancy row memory array for storage and retrievalwhen the address signal specifies the main memory defective celladdress, and said decoding means and said detecting means receiving theaddress signal simultaneously, so that detection occurs coincident withdecoding.